Boole-Deusto is available for download here. The latest version is BooleDeusto Jan. 2014 (English)

Boole-Deusto is Open Source. Traditionally it has been hosted in SourceForge, but for the latest versions we have moved to a GitHub repository.

Boole-Deusto is an educational software tool for Digital Electronics. Digital electronic circuits can be classified in two large groups: combinational and sequential circuits, depending on whether they have a memory (and are hence sequential) or not. Boole-Deusto supports both types, as long as they are bit-level.

Unlike other, sometimes more advanced tools, Boole-Deusto is especially oriented for students. Focusing on the design process, students can use Boole-Deusto through every step in a digital circuit's design, getting involved only to the extent they (or their teacher) desires. That is, it can be used to generate a circuit straightaway, or it can walk through every step involved (such as Karnaugh Maps and logic simplification).

Install

Boole-Deusto is distributed as a compressed executable, with no dependencies. Thus, no installation is really required. You can simply:

1. Download the Boole-Deusto latest package.
2. Extract the files using your favourite compression tool (such as the default Windows extractor, WinRar or 7zip).
3. Run boole.exe.

Quickstart Guide

Boole-Deusto can be used to design, implement and test (through the Weblab Remote Laboratory) logical systems. It mainly supports two types of systems:

• Bit-level combinational systems
• Bit-level finite state machines (FSMs)

Though Boole-Deusto offers many tools for each kind of system, the basics are relatively straightforward. Here we will describe, as an example, the steps that you need to follow to design, implement and test a basic combinational system.

Design & Implementation

Note: Before you start, write a problem statement or a definition of your system. It is advisable to have a clear idea of what you want your system to accomplish before getting started.

1. Open the Combinational Systems editor in Boole-Deusto, and start by giving your system a name.
2. Mark the Weblab-Deusto Mode checkbox if it is not checked already. Otherwise, the code generated by Boole-Deusto will not be compatible with Weblab-Deusto.
3. Choose the number of inputs and outputs that you want your system to have.
4. Assign names to the inputs and outputs. Choose from the list of WebLab names, do not write your own.
5. Define the truth-table of the system. Do not forget to save after defining the truth table. Leave no entries blank: all must be either 0, 1 or X (which indicates that the value doesn’t matter and makes certain optimizations possible).
6. The system is ready. You may want to check the equivalent logic circuit or the simplified boolean expressions.

Note: The workflow that has been described here the simplest possible. Many intermediate steps, such as boolean expression simplifications, are here carried out by Boole-Deusto itself. This, however, is somewhat contrary the point of the tool. Many users will want to carry out these steps themselves through the use of tools such as the Karnaugh diagrams, which are also supported.

Testing with Weblab-Deusto

Note: For testing with Weblab-Deusto, you may require certain Weblab-Deusto privileges. If access to the FPGA experiment is not available, please ask the administrators.

Weblab-Deusto is a remote laboratory which offers access to many remote experiments. Among those experiments we have:

• FPGA boards
• PLD boards

Boole-Deusto integrates closely with these, and is able to generate VHDL code that is immediately compatible with Weblab and with those laboratories. To do so:

1. Ensure that the Weblab Mode checkbox is checked.
2. Click on the Open FPGA button.
3. Choose to generate VHDL code when you are asked to. Remember where you save it.
4. A browser should open and load *Weblab-Deusto FPGA (you may need to login first).
5. Choose the VHDL file that you saved a few steps back.
6. Wait a few minutes for the VHDL to be synthesized. Once the system is ready, Weblab will be executing your logic, and you can interact freely with the FPGA board.