| 2025-03-25 08:08:19Z.487885 |
2025-03-25 08:08:19Z.495744 |
@@@initial::request@@@ |
{"back": "https://weblab.deusto.es/weblab/labs/PIC%20experiments/ud-logic/?finished=true"} |
N/A |
| 2025-03-25 08:08:19Z.487885 |
2025-03-25 08:08:19Z.495744 |
@@@initial::response@@@ |
{ "webcam" : "https://www.weblab.deusto.es/webcam/logic0/image.jpg?size=2" } |
N/A |
| 2025-03-25 08:08:19Z.690067 |
2025-03-25 08:08:19Z.698467 |
GET_CIRCUIT |
{"op": "or", "right": {"op": "nor", "right": {"op": "nor", "right": true, "left": true}, "left": {"op": "nand", "right": true, "left": false}}, "left": {"op": "nor", "right": {"op": "nand", "right": true, "left": false}, "left": {"op": "or", "right": false, "left": true}}} |
N/A |
| 2025-03-25 08:08:27Z.691536 |
2025-03-25 08:08:27Z.698888 |
SOLVE nand |
FAIL |
N/A |
| 2025-03-25 08:08:29Z.776382 |
2025-03-25 08:08:29Z.782625 |
@@@finish@@@ |
0 |
N/A |