| 2026-05-20 16:42:57Z.721671 |
2026-05-20 16:42:57Z.729335 |
@@@initial::request@@@ |
{"back": "https://weblab.deusto.es/weblab/labs/PIC%20experiments/ud-logic/?finished=true"} |
N/A |
| 2026-05-20 16:42:57Z.721671 |
2026-05-20 16:42:57Z.729335 |
@@@initial::response@@@ |
{ "webcam" : "https://www.weblab.deusto.es/webcam/logic0/image.jpg?size=2" } |
N/A |
| 2026-05-20 16:42:58Z.765584 |
2026-05-20 16:42:58Z.777211 |
GET_CIRCUIT |
{"op": "nand", "right": {"op": "xor", "right": {"op": "nand", "right": false, "left": false}, "left": {"op": "nand", "right": false, "left": false}}, "left": {"op": "xor", "right": {"op": "nand", "right": false, "left": false}, "left": {"op": "nor", "right": false, "left": false}}} |
N/A |
| 2026-05-20 16:43:23Z.252981 |
2026-05-20 16:43:23Z.257901 |
SOLVE or |
FAIL |
N/A |
| 2026-05-20 16:43:28Z.272261 |
2026-05-20 16:43:28Z.279592 |
@@@finish@@@ |
0 |
N/A |