| 2026-05-18 16:52:48Z.433014 |
2026-05-18 16:52:48Z.442721 |
@@@initial::request@@@ |
{"back": "https://weblab.deusto.es/weblab/labs/PIC%20experiments/ud-logic/?finished=true"} |
N/A |
| 2026-05-18 16:52:48Z.433014 |
2026-05-18 16:52:48Z.442721 |
@@@initial::response@@@ |
{ "webcam" : "https://www.weblab.deusto.es/webcam/logic0/image.jpg?size=2" } |
N/A |
| 2026-05-18 16:52:48Z.639108 |
2026-05-18 16:52:48Z.645926 |
GET_CIRCUIT |
{"op": "xor", "right": {"op": "or", "right": {"op": "nor", "right": true, "left": true}, "left": {"op": "nand", "right": true, "left": true}}, "left": {"op": "or", "right": {"op": "nand", "right": true, "left": true}, "left": {"op": "and", "right": true, "left": true}}} |
N/A |
| 2026-05-18 16:52:55Z.486418 |
2026-05-18 16:52:55Z.492993 |
SOLVE and |
FAIL |
N/A |
| 2026-05-18 16:52:58Z.621198 |
2026-05-18 16:52:58Z.629303 |
@@@finish@@@ |
0 |
N/A |