| 2026-05-17 16:02:53Z.600945 |
2026-05-17 16:02:53Z.608146 |
@@@initial::request@@@ |
{"back": "https://weblab.deusto.es/weblab/labs/PIC%20experiments/ud-logic/?finished=true"} |
N/A |
| 2026-05-17 16:02:53Z.600945 |
2026-05-17 16:02:53Z.608146 |
@@@initial::response@@@ |
{ "webcam" : "https://www.weblab.deusto.es/webcam/logic0/image.jpg?size=2" } |
N/A |
| 2026-05-17 16:02:54Z.321198 |
2026-05-17 16:02:54Z.333537 |
GET_CIRCUIT |
{"op": "nand", "right": {"op": "or", "right": {"op": "xor", "right": true, "left": true}, "left": {"op": "nand", "right": true, "left": false}}, "left": {"op": "or", "right": {"op": "nand", "right": true, "left": false}, "left": {"op": "nor", "right": false, "left": false}}} |
N/A |
| 2026-05-17 16:03:03Z.292923 |
2026-05-17 16:03:03Z.301354 |
SOLVE or |
FAIL |
N/A |
| 2026-05-17 16:03:03Z.899891 |
2026-05-17 16:03:03Z.907612 |
@@@finish@@@ |
0 |
N/A |