| 2026-04-08 11:24:34Z.733105 |
2026-04-08 11:24:34Z.759590 |
@@@initial::request@@@ |
{"back": "https://weblab.deusto.es/weblab/labs/PIC%20experiments/ud-logic/?finished=true"} |
N/A |
| 2026-04-08 11:24:34Z.733105 |
2026-04-08 11:24:34Z.759590 |
@@@initial::response@@@ |
{ "webcam" : "https://www.weblab.deusto.es/webcam/logic0/image.jpg?size=2" } |
N/A |
| 2026-04-08 11:24:35Z.422676 |
2026-04-08 11:24:35Z.497359 |
GET_CIRCUIT |
{"op": "xor", "right": {"op": "and", "right": {"op": "nor", "right": true, "left": false}, "left": {"op": "nand", "right": false, "left": false}}, "left": {"op": "nor", "right": {"op": "nand", "right": false, "left": false}, "left": {"op": "nor", "right": false, "left": true}}} |
N/A |
| 2026-04-08 11:25:49Z.134861 |
2026-04-08 11:25:49Z.142160 |
SOLVE nand |
FAIL |
N/A |
| 2026-04-08 11:25:50Z.684866 |
2026-04-08 11:25:50Z.691657 |
@@@finish@@@ |
0 |
N/A |