| 2026-04-08 11:22:11Z.048612 |
2026-04-08 11:22:11Z.499823 |
@@@initial::request@@@ |
{"back": "https://weblab.deusto.es/weblab/labs/PIC%20experiments/ud-logic/?finished=true"} |
N/A |
| 2026-04-08 11:22:11Z.048612 |
2026-04-08 11:22:11Z.499823 |
@@@initial::response@@@ |
{ "webcam" : "https://www.weblab.deusto.es/webcam/logic0/image.jpg?size=2" } |
N/A |
| 2026-04-08 11:22:12Z.501808 |
2026-04-08 11:22:12Z.565302 |
GET_CIRCUIT |
{"op": "nand", "right": {"op": "or", "right": {"op": "xor", "right": true, "left": true}, "left": {"op": "nand", "right": true, "left": false}}, "left": {"op": "nand", "right": {"op": "nand", "right": true, "left": false}, "left": {"op": "nor", "right": false, "left": true}}} |
N/A |
| 2026-04-08 11:24:21Z.251511 |
2026-04-08 11:24:21Z.258094 |
SOLVE xor |
FAIL |
N/A |
| 2026-04-08 11:24:23Z.551834 |
2026-04-08 11:24:23Z.599490 |
@@@finish@@@ |
0 |
N/A |