| 2026-01-26 16:22:22Z.728845 |
2026-01-26 16:22:22Z.738431 |
@@@initial::request@@@ |
{"back": "https://weblab.deusto.es/weblab/labs/PIC%20experiments/ud-logic/?finished=true"} |
N/A |
| 2026-01-26 16:22:22Z.728845 |
2026-01-26 16:22:22Z.738431 |
@@@initial::response@@@ |
{ "webcam" : "https://www.weblab.deusto.es/webcam/logic0/image.jpg?size=2" } |
N/A |
| 2026-01-26 16:22:23Z.060836 |
2026-01-26 16:22:23Z.068325 |
GET_CIRCUIT |
{"op": "nand", "right": {"op": "xor", "right": {"op": "and", "right": true, "left": false}, "left": {"op": "nand", "right": false, "left": true}}, "left": {"op": "xor", "right": {"op": "nand", "right": false, "left": true}, "left": {"op": "nor", "right": true, "left": false}}} |
N/A |
| 2026-01-26 16:23:09Z.539554 |
2026-01-26 16:23:09Z.550545 |
SOLVE nand |
FAIL |
N/A |
| 2026-01-26 16:23:13Z.346460 |
2026-01-26 16:23:13Z.355747 |
@@@finish@@@ |
0 |
N/A |