| 2026-01-02 14:37:21Z.244010 |
2026-01-02 14:37:21Z.251161 |
@@@initial::request@@@ |
{"back": "https://weblab.deusto.es/weblab/labs/PIC%20experiments/ud-logic/?finished=true"} |
N/A |
| 2026-01-02 14:37:21Z.244010 |
2026-01-02 14:37:21Z.251161 |
@@@initial::response@@@ |
{ "webcam" : "https://www.weblab.deusto.es/webcam/logic0/image.jpg?size=2" } |
N/A |
| 2026-01-02 14:37:21Z.584097 |
2026-01-02 14:37:21Z.593871 |
GET_CIRCUIT |
{"op": "nand", "right": {"op": "or", "right": {"op": "and", "right": false, "left": false}, "left": {"op": "nand", "right": false, "left": false}}, "left": {"op": "or", "right": {"op": "nand", "right": false, "left": false}, "left": {"op": "nand", "right": false, "left": false}}} |
N/A |
| 2026-01-02 14:37:37Z.414729 |
2026-01-02 14:37:37Z.422496 |
SOLVE nor |
FAIL |
N/A |
| 2026-01-02 14:37:41Z.624943 |
2026-01-02 14:37:41Z.632817 |
@@@finish@@@ |
0 |
N/A |