| 2025-09-12 21:21:34Z.563457 |
2025-09-12 21:21:34Z.572639 |
@@@initial::request@@@ |
{"back": "https://weblab.deusto.es/weblab/labs/PIC%20experiments/ud-logic/?finished=true"} |
N/A |
| 2025-09-12 21:21:34Z.563457 |
2025-09-12 21:21:34Z.572639 |
@@@initial::response@@@ |
{ "webcam" : "https://www.weblab.deusto.es/webcam/logic0/image.jpg?size=2" } |
N/A |
| 2025-09-12 21:21:35Z.406786 |
2025-09-12 21:21:35Z.413697 |
GET_CIRCUIT |
{"op": "or", "right": {"op": "nor", "right": {"op": "nand", "right": false, "left": false}, "left": {"op": "nand", "right": false, "left": true}}, "left": {"op": "nor", "right": {"op": "nand", "right": false, "left": true}, "left": {"op": "xor", "right": true, "left": true}}} |
N/A |
| 2025-09-12 21:22:57Z.592978 |
2025-09-12 21:22:57Z.600182 |
SOLVE nand |
FAIL |
N/A |
| 2025-09-12 21:23:00Z.363300 |
2025-09-12 21:23:00Z.371257 |
@@@finish@@@ |
0 |
N/A |